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Dual/Quad PCM Bit Sync/ BSS Data Quality Encapsulator

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Note: The MD2265EC Bit Synchronizer is intended only for Best Source Selector (BSS) applications. For non-BSS use, select the MD2265 (non-EC model)

The GDP Model 2265EC Multi-Channel PCM Bit Synchronizer / BSS Data Quality Encapsulator (DQE) houses up to 4 high-performance bit synchronizer channels in a 2U chassis. The optimized digital design of this unit affords the highest performance characteristics currently available. This unit can be used as a stand-alone bit synchronizer and as a BSS Data Quality Encapsulator for the GDP Diversity Combining / Best Source Selector products. When used as a BSS Encapsulation unit, the BS input must be connected to the baseband analog output of the receiver so that data quality can be determined

The Model 2265EC is capable of maintaining synchronization with the signal of interest down to –3 dB Eb/No at signal levels as low as 100mVp -p. When searching for the signal, acquisition is attainable in less than 50 bits. The unit can maintain synchronization for a period of at least 256 bit periods without a transition.

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GDP 2265EC

Key Features

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Highest Performance Characterisitcis on the market

Best Source Selection Data Quality Encapsulation (DQE) Output FMTS: GDP Type 1 DQE, GDP Type 2 DQE

2 & 4 Channel Configurations

Bit Rates: 5 bps to 40 Mbps

Performance: Within 1 dB of theory, advanced lock detection down to -3dBEb/No

Loop Bandwidth: 0.01% to 1.6% (Extended Range Optional)

The standard IRIG randomizer/derandomizer (others are optionally available) for both forward and reverse sequences is provided. CCITT V.35 and V.36 scrambling/ descrambling is also provided. A variety of Viterbi decoders are available, including R1/2 K7 (Std), R3/4 K7 (opt), and R1/3 K7 (opt)  (inquire for other FEC options).

To assure synchronization with the intended data stream, the Frame Pattern Detector may be invoked. Up to a 64bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. An Automatic Polarity Correction (APC) mode is provided for inverted data.

The Encapsulator assembles reconstructed data and data quality information into a GDP DQE transfer frame (ENCAPSULATION). This transfer frame is suitable for passage by way of a data link to a GDP Best Source Selector. In this way, the data quality information that is available at the first point of signal reception is passed to a remote location where the Best Source Selector makes its decisions.

The MD2265EC includes several unique features to determine the quality of the data. The first is an Eb/No (Signal Quality) measurement. From this measurement, the error rate of the data can be determined. The MD2265EC also determines BER from an embedded PCM frame synchronizer pattern, if present, as well as BER from the Viterbi stream when these modes are enabled. A bit-error-rate (BERT) function is also provided that allows link test in a short loop-back to verify proper operation of the module, or long loop-back to measure performance of the link. An advanced lock detector ensures a solid lock indication for the bit synchronizer.

Each of the channels includes three Analog inputs. Each channel provides outputs that include: TTL Coded PCM & TTL Encapsulated output. Each data output is associated with a coherent clock that is programmable to 0, 90, 180, and 270 degrees.

 

Additional Features

Supports NRZ-L/M/S, BiØ-L/M/S, DM-M/S, MDM-M/S.

Data Quality Status: Eb/No, Bit Error Rate (BER), and Convolutional Error Rate (CER).

Input Signal Status: Sync/Signal Loss, Bit Rate, Signal Level, Data Polarity, Eb/No.

FEC: Viterbi Decoder & Convolution Encoder

QOSK Support: OPSK/OQPSK/SOQPSK

Error Checking: Built-in BERT & Frame Sync Pattern Detector

Randomizer/Derandomizer & Scrambler/Descrambler: CCITT V.35/V.36.

Frame Pattern Detector

Input Signal Status:

  • Sync and Signal Loss
  • Measured Input Bit Rate
  • Measured Signal Level
  • Input Data Polarity

Signal/Data Quality Status

  • Eb/No Measurement
  • BER / CER Measurement BERT PRN
  • Signal Level Measurement

Data Generator/Simulator

  • Serial and QPSK

Remote Control via. Ethernet & RS232

WHY YOU SHOULD BUY YOUR NEXT BIT SYNCHRONIZER FROM GDP

THE GOLD STANDARD FOR BIT SYNCHRONIZERS

As you may already know, GDP Space Systems is an industry leader in the development and manufacture of high-performance Bit Synchronizers and other telemetry and signal acquisition products. We pride ourselves on performance, quality, service, and customer support.

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Ordering Options

Base

MD2265-M02-EC Dual Channel PCM Bit Synchronizer / BSS DQE Encapsulator
Including:

  • GDP Type 1 DQE BSS Output Format
  • GDP Type 1 DQE BSS Output Format
  • 40Mbps Operation
  • Frame Sync Pattern Detector
  • Viterbi Decoder (K=7;Rate 1/2)
  • Built-in BERT Function
  • Ethernet Remote Control
  • 75 Ohm
  • Chassis Slides
MD2265-M04-EC Quad Channel PCM Bit Synchronizer / BSS DQE Encapsulator
Including:

  • GDP Type 1 DQE BSS Output Format
  • GDP Type 1 DQE BSS Output Format
  • 40Mbps Operation
  • Frame Sync Pattern Detector
  • Viterbi Decoder (K=7;Rate 1/2)
  • Built-in BERT Function
  • Ethernet Remote Control
  • 75 Ohm
  • Chassis Slides

Options

OP2265EC-50 Redundant Power Supply

Spares

BSM004-MSTR Dual Channel Bit Synchronizer/BSS Data Encapsulation Module-Master
BSM004-SLAV Dual Channel Bit Synchronizer/BSS Data Encapsulation Module-Slave
DSPLY2265 Spare Front Panel Display (Spare)
OP2265EC-PWR-NR Power Supply Only (Non-redundant)
OP2265EC-PWR-RD Power Supply and Redundant Power Board

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